This invention relates to the field of digital integrated circuits and more specifically to the field of programmable logic array (PLA) integrated circuits.
Programmable logic array circuits such as the circuits described in the "PAL Programmable Array Logic Handbook" published by Monolithic Memories, Inc., in 1983 are well known in the art. (PAL is a registered trademark of Monolithic Memories, Inc., the Assignee of this application.) FIG. 1 illustrates a simple PLA circuit 10. Included in circuit 10 are four input terminals I.sub.0 through I.sub.3, each of which is coupled to the input lead of a buffer B0 through B3, respectively. Each buffer has an inverting output lead and a noninverting output lead. For example, buffer B0 has an output lead 12a which provides a signal ISO, which is the inverse of the signal present on terminal I.sub.0. Similarly, buffer B0 has an output lead 12b, which provides a signal IS0, which is equal to the signal present at terminal I.sub.0. Each of the output signals from buffers B0 to B3 is presented as an input signal to an AND gate 14a. AND gate 14a is an 8-input AND gate, and each of the output leads of buffers B0 to B3 is uniquely coupled to a single input lead of AND gate 14a. Thus, FIG. 2a illustrates the eight input leads to AND gate 14a. FIG. 2b illustrates AND gate 14a using the more conventional notation. In addition, fifteen other AND gates 14b to 14p are also connected to the output leads of buffers B0 through B3 in the same manner as AND gate 14a. Thus, each of AND gates 14a to 14p is coupled to all eight output leads of buffers B0 to B3. However, a purchaser of a PLA circuit has the option of severing the connection between a given buffer output lead and a given AND gate 14a to 14p. In some prior art circuits, this is done by opening a fuse similar to the fuses employed in programmable read only memories. In other prior art circuits this is done during the manufacturing process of the circuit. Regardless of how such connections are severed, the user can cause each AND gate 14a through 14p to provide a unique output signal dependent on a particular set of input signals. The output signals from AND gates 14a through 14p are sometimes referred to as the "product terms". (As used herein the expression "product term" means the logical product resulting from a logical AND operation on a plurality of input signals, e.g., SIGNAL.sub.1 .multidot.SIGNAL.sub.2, while the expression "sum term" means the logical sum, resulting from a logical OR operation performed on a plurality of input signals, e.g., SIGNAL.sub.1 +SIGNAL.sub.2.)
Also, as can be seen in FIG. 1, a first OR gate 16a includes four input leads coupled to the output leads of AND gates 14m, 14n, 14o and 14p. OR gate 16a generates an output signal on an output lead O.sub.0 therefrom. Similarly, an OR gate 16b receives output signals from AND gates 14i, 14j, 14k, and 14l and generates an output signal on a lead O.sub.1 therefrom. In this way, programmable circuit 10 provides desired programmable Boolean functions which can be used in a variety of applications. As used in this specification, a programmable logic circuit which provides "desired programmable Boolean functions" is one which can be programmed by the system designer to provide any of a number of Boolean functions required in a given system design. This semicustom circuit provides an inexpensive replacement for a large number of logic circuits which would otherwise be required. As is known in the art, different generic types of PLA circuits include different numbers of input terminals and different numbers of output terminals.
Another type of PLA circuit is PLA 19 illustrated in FIG. 3. The array of OR gates 20a through 20d of PLA 19 are electrically programmably coupled to the output leads of AND gates 14a through 14p (i.e., the electrical connection between an AND gate and an OR gate can be severed). This is in contrast to PLA circuit 10 of FIG. 1 in which the sources of input signals for OR gates 16a through 16d are fixed and nonprogrammable.
However, PLA's including OR gates with programmable inputs have a number of disadvantages, e.g., they consume a large amount of surface area because of the need to provide additional circuitry to program the OR gate inputs. In addition, the presence of a large number of input leads to an OR gate creates a large capacitance which slows the OR gate.